1. Field of the Invention
The invention disclosed herein relates generally to a nonvolatile memory device, and more particularly, but without limitation, to a method of driving a nonvolatile memory device.
2. Description of the Related Art
Nonvolatile memory devices retain data stored in cells even if power is not supplied. Flash memory devices are one type of nonvolatile memory. Since flash memory devices electrically erase a block of data cells at a time, flash memory devices are being widely used in computers, memory cards, etc.
Such a flash memory device is classified into a NOR flash memory and a NAND flash memory. One distinction between NOR flash memory and NAND flash memory relates to how memory cells are connected to a bitline. In general, the NOR flash memory device is advantageous in high-speed performance, whereas it is disadvantageous in high integration due to its high current consumption. The NAND flash memory device is advantageous in high integration because it consumes smaller amount of current than the NOR flash memory device.
FIG. 1 is a circuit diagram of a memory cell array 110 using a double patterning technique (DPT). Generally, the DPT is a patterning technique to overcome a limitation of a photolithographic apparatus. According to the DPT, the memory cell array is formed in such a way that even-numbered patterns are formed first and odd-numbered patterns are thereafter formed.
FIGS. 2A through 2C are pictorial illustrations of shapes and configurations of wordlines and bitlines in FIG. 1. Specifically, FIG. 2A is a sectional view illustrating a channel of a memory cell, which is taken along line A-A′ of FIG. 1. Referring to FIG. 2A, a channel width of a wordline differs according to whether the wordline is an even-numbered one or an odd-numbered one. Herein, the even-numbered wordline has a channel width Lg1 that is smaller than a channel width Lg2 of the odd-numbered wordline. FIG. 2B is a sectional view illustrating a width of an active region of a memory cell, which is taken along line B-B′ of FIG. 1. Referring to FIG. 2B, an active region of an even memory cell has a width AW1 that is smaller than a width AW2 of an active region of an odd memory cell. FIG. 2C illustrates metal widths of odd and even-numbered bitlines. Referring to FIG. 2C, the even-numbered bitline has a width BW1 that is smaller than a width BW2 of the odd-numbered bitline.
FIG. 3 is a graphical illustration of threshold voltage distributions of memory cells manufactured according to the DPT. Referring to FIG. 3, there is a difference in threshold voltage distribution according to whether the memory cell is an even-numbered cell or an odd-numbered cell. Herein, the even-numbered memory cell means a memory cell connected to the even-numbered wordline, and the odd-numbered memory cell means a memory cell connected to the odd-numbered wordline. In a typical nonvolatile memory device performing a program operation according to an incremental step pulse programming (ISPP) method, however, program operating conditions, for example, a program start voltage (Vo), an ISPP incremental level (ΔISPP) and a program stop voltage (Vm), are determined from a total distribution irrespective of whether the memory cell is an odd-numbered cell or and even-numbered cell. Here, the program operating conditions satisfy following Equations 1 and 2.Vm=Vo+mΔISPP  (Equation 1)ΔVw=Vm−V0  (Equation 2)where m is an iteration number of a program loop for reaching a program stop voltage (Vm).
As illustrated in FIG. 3, the total distribution is relatively broader than the distribution of even-numbered memory cells and odd-numbered memory cells. Consequently, it is difficult for the typical nonvolatile memory device to have an optimized programming time because the program operating conditions are determined from the total threshold voltage distribution. This is because the programming time is proportional to the width of the threshold voltage distribution in general. Further, the width (ΔVw) of the distribution becomes great in ISPP operation, and hence the iteration number (m) of the program loop increases correspondingly. This leads to an increase in stress of a memory cell, resulting in deterioration of reliability of the memory cell in the long run.
FIG. 4 is an equivalent circuit diagram and an associated voltage-time curves for a conventional bitline structure and sensing method. The width of the bitline differs according to whether the bitline is an odd-numbered bitline or even-numbered bitline, as illustrated in FIG. 2C. Referring to FIG. 4, therefore, parasitic resistance and capacitance also differ according to whether the bitline is an odd-numbered bitline or an even-numbered bitline. That is, a parasitic resistance Re of the even-numbered bitline is greater than a parasitic resistance Ro of the odd-numbered bitline, and a parasitic capacitance Ce of the even-numbered bitline is smaller than a parasitic capacitance Co of the odd-numbered bitline. This is attributed to the fact that the width BW1 of the even-numbered bitline is smaller than the width BW2 of the odd-numbered bitline. This may cause a RC time constant to differ according to whether the bitline is an odd-numbered bitline or even-numbered bitline. For convenience in description, it is assumed that an RC time constant (ReCe) of the even-numbered bitline is greater than an RC time constant (RoCo) of the odd-numbered bitline.
As a result, sensing operating conditions (e.g., precharge time, development time) will differ according to whether the bitline is the even-numbered bitline or the odd-numbered bitline. Herein, the precharge time refers to a time taken for a bitline voltage to rise up to a precharge voltage, e.g., a power supply voltage. The development time refers to a time taken for the bitline voltage to drop to a trip voltage Vtrip from the precharge voltage. If the bitline is an even-numbered bitline, the precharge time is shorter than that of the odd-numbered bitline, and the development time is longer than that of the odd-numbered bitline. On the contrary, if the bitline is an odd-numbered bitline, the precharge time is longer than that of the even-numbered bitline, and the development time is shorter than that of the even-numbered bitline. However, the typical nonvolatile memory device operates with the same sensing operating condition regardless of whether the bitline is an even-numbered bitline or an odd-numbered bitline.
That is, under the sensing operating condition of the typical nonvolatile memory device, a sensing time Ts is determined such that it includes both the precharge time Tpc of the odd-numbered bitline which is relatively longer than that of the even-numbered bitline and a development time Td of the even-numbered bitline which is relatively longer than that of the odd-numbered bitline. As illustrated in FIG. 4, waiting times Tw1 and Tw2 take place in the even-numbered and odd-numbered bitlines, respectively. That is, the typical nonvolatile memory device cannot optimize a sensing time.
Referring to FIG. 4 again, in a precharge operation of the even-numbered bitline BLe, the even-numbered bitline BLe is precharged faster than the odd-numbered bitline BLo. However, the precharge time Tpc is limited by the precharge time of the odd-bitline BLo. In a development operation of the odd-numbered bitline BLo, the odd-numbered bitline BLo is developed faster than the even-numbered bitline BLe. In this case, however, a cell current development time Td is limited by the development time of the even-numbered bitline BLe. This leads to degradation in read/verify characteristics of a nonvolatile memory device. Improved nonvolatile memory device structures are therefore needed.